该职位来源于猎聘 关键要求:电子工程硕士,3年以上CCD/CIS模拟电路设计 Job Responsibilities:
- Design, analyze, and implement high-performance (>10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, ToF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
- The design of high-frequency (multi-gigahertz) and high-precision clocking and analog circuits.
- Use EDA tools (Cadence, Mentor) to run simulation and function verification.
- Guide layout engineer to optimize layout.
- Chip debug and testing individually and with the team. [6] Other tasks assigned by line manager. Qualifications:
- MSEE in analog IC design with no less than 1 years experience. Exceptional fresh Master or PHD is considered.
- Experience in Cadence EDA tools.
- Team player with good communication skills.
- Experience with multi-gigahertz SERDES transmitter/receiver, TIA, PLL, CDR, LNA etc. is highly preferred.
- Desired: Knowledge of advanced circuits such as PLLs, ADCs, DACs, LNAs, drivers, NF, S-parameters, BW extension, impedance matching.
- Desired: Experience in RF circuit design, testing, and post-silicon bring-up and evaluation.