- Expertise in physical design implementation of large ASICs (100 to 400 million gates complexity)
- Expertise in technical hands-on competency in using leading edge physical design EDA tools in projects
- (Cadence tool)
- Expertise in CPU / DSP architecture / algorithm
- Expertise in top end physical design implementation
- Expertise in EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 12nm* / 7nm* / 5nm / 3nm / 2nm process technologies
- Expertise in one or more VLSI design tools for Place & Route, verilog simulation, DRC/LVS verification, timing analysis, scripting languages
- Expertise in Linux / Unix scripting
- VISA SPONSORED