该职位来源于猎聘 THE PERSON:
Candidate will work as IP design/Arch engineer in CF team on development of industry leading chiplet fabric. KEY RESPONSIBILITIES:
- Block level and subsystem level micro-architecture, RTL design, static verification, synthesize and timing closure
- Deliver CF high quality IP to SoCs, meet power, area, timing, schedule bounding box, and other metrics
PREFERRED EXPERIENCE:
- Good experience on system IP design in complex SoC, system reset and boot, advanced power management, clocking and etc
- Strong skills on Verilog HDL or System Verilog
- Strong knowledge on AMBA(AXI/AHB/APB) bus
- Familiar with Front-End design and implementation flow
- Knowledge on synthesis, STA, CDC
- Network-on-chip experience is a plus
- Strong analytical and problem-solving skills
- Excellent communication skills and experience collaborating with global projects colleague
- Low power design experience is a plus
- Good skills on Perl/Python script
- Exposure to leadership or mentorship is an asset
- Fluent English communication skills(listening, speaking and writing)
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in computer engineering/Electrical Engineering