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Analog Design Engineer 模拟设计工程师
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Responsibilities
- You will design, analyze, and implement high-performance (>10GHz) PLL, wireline amplifiers, CDR, SERDES, PLL, PAM4, TDCs, TOF, low-noise amplifiers, transmitters, power-amplifiers and power-drivers, or other baseband circuits like LDO, temp sensor, ADC, Filters, etc.
- Use EDA tools (Cadence, Mentor) to run simulation and function verification.
- Guide layout engineer to optimize layout.
- Chip debug and testing individually and with the team.
- Other tasks assigned by line manager.
Qualifications
- MSEE in analog IC design.
- Hands-on design experience with multi-gigahertz SERDES transmitter/receiver, TIA, PLL, CDR, LNA, ToF, Temperature Sensor, power management IC or low-speed ADC/amplifier.
- Great team management skills.
- Experience in Cadence EDA tools.
- Team player with good communication skills.
Location: Shanghai, Shenzhen
要求:电子工程硕士,2年以上模拟电路设计,擅长SerDes等高速接口,TIA, PLL, CDR, LNA, ToF, Temperature Sensor, PMIC(DC-DC Boost/Buck) 低速ADC/放大器等任一领域。欢迎应届硕士、博士。
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