该职位来源于猎聘 At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: FE Design Engineer Location: Shanghai or Nanjing, China Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage
- The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
- Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
- The unique "One Cadence – One Team" culture promotes collaboration within and across teams to ensure customer success.
- Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
- You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day. Job Summary: Join a growing and dynamic organization developing the proliferation of best-in-class physical IP for industry-standard protocols. This is a tremendous opportunity to work with an experienced and full skillset team focusing on high-performance IP AND to engage with technology sector's top companies making an impact in our world. Primary Responsibilities: Key contributor in the IP frontend design team, especially on high-performance Consumer PHYs including eUSB/USB, MIPI C/D/M-PHY, ONFI, eDP/DP, SATA, etc. Work with digital verification team to specify coverage points, testing strategy, corner conditions, stimulus creation and FPGA/Palladium testing Work with wider engineering and IP delivery/release teams to develop and use infrastructure to integrate IPs into subsystems and QA for customer releases Position Requirements: MS / BS in Electrical/Computer Engineering or related degree. 3+ years of relative industry working experience, in ASIC design role for delivering advanced IP and/or ASIC/SOC products. Knowledge of best practices and flows in Design Architecture, RTL design/verification and ASIC end-to-end methodology. Knowledge of one or more industry serial standards, such as USB, MIPI, PCIe, Ethernet, etc. Understanding basics of Analog Mixed-Signal, SI/PI, Post-Silicon Validation, and system view of physical interface IPs and their typical applications. Show customer success first attitude and empathy and drive internal teams to meet or exceed customer expectations. One Team mentality with a passion to innovate and can-do attitude. Strong cross-functional communication skills in both English and Mandarin. Self-starter and highly motivated. Qualifications as Plus Direct experience of high-speed serial interface link IPs in advanced technology nodes. Knowledge of multiple programming languages, System Verilog, Python, C/C++, etc. Knowledge of embedded microcontroller or DSP usage and FW. Experience with various Cadence ASIC design tools.