- Physical Design Engineer
- Experience : Years
- Job Location : Beijing OR Shanghai
- Considering Chinese Citizens Only
You may connect with me on :
Applicants may submit CV direct to Email : sunil.-
Job Responsibilities
- Responsible for the full-process work of SOC chips and ASIC chips from netlist to tape-out.
- Cooperate with front-end engineers to complete floorplan, CTS (Clock Tree Synthesis), and Routing tasks.
- Communicate with designers to complete the writing or modification of SDC (Synopsys Design Constraints).
- Responsible for area optimization, power consumption optimization, timing optimization, IR drop analysis, as well as module-level STA (Static Timing Analysis) and PV (Physical Verification) signoff-related work.
- Master processes such as placement, clock tree synthesis and routing in the physical design flow, and have a basic foundation in back-end physical verification and formal verification.
- Conduct timing analysis for back-end design and optimize chip area and power consumption from the perspective of implementation.
Job Qualifications
- Bachelor's degree or above in Microelectronics, Electronic Engineering, Communications, Computer Science or related majors; priority will be given to candidates with more than 2 years of back-end design-related work experience.
- Master the basics of digital circuit analysis and be familiar with scripting languages.
- Proficient in P&R (Placement and Routing) flow tools of Synopsys or Cadence.
- Skilled in script writing (Perl, Tcl).
岗位职责: 1、负责SOC芯片、ASIC芯片从netlist到tap-out的全流程工作; 2.与前端工程师配合,完成floorplan,CTS,Routing工作。 3.与设计人员沟通,完成SDC的编写或者修改。 4.负责面积优化,功耗优化,时序优化,IR drop分析,以及完成模块级的STA与PV signoff相关工作. 5、掌握物理设计流程中的布局、时钟树综合布线等流程,并对后端物理验证和形式验证有设计基础; 6、针对后端设计能够进行时序分析,并从实现的角度优化芯片面积和功耗。
任职资格: 1、微电子/电子工程/通信/计算机等相关专业本科及以上学历;后端设计相关工作经验2年以上优先; 2、掌握数字电路分析基础,熟悉脚本语言; 3、精通synopsys或cadence公司P&R流程工具; 4、熟练的脚本编写技能(perl、tcl) ;