At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Design Engineer II - Verification
Location: Beijing, China
Job Description
Cadence/Tensilica is a leading provider of configurable embedded processor technology and DSPs for various markets. As a member of the DSP engineering group you will be responsible for verification of advanced DSP cores and their instruction set architectures and hardware implementations.
- Implement architectural simulation testbenches in C/C++/RTL, write C/assembly language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
- Assist with developing test plans, debugging failures and analyzing coverage information.
- Work closely with the market-specific DSP teams, Design Verification, and RTL and EDA teams.
Qualifications
- Master in Electronics, Computer Science or related major, Bachelor with equivelant working experience.
- Knowledge of DSPs, instructions sets, computer arithmetic concepts, and processor architecture concepts
- Good knowledge of C (C++ will be a plus)
- Working knowledge of Verilog and popular EDA simulators and testbench methodologies
- Knowledge of scripting languages such as Makefile/Perl is desired
- Knowledge of assembly programming and programming in a high level language such as C will be a plus
- Good English communication skills - both written and verbal
- Strong problem solving skills along with an ability to work independently and in cooperation with global teams
We're doing work that matters. Help us solve what others can't.